Reprints from my posting to SAN-Tech Mailing List and ...


[Links]: Intel Xeon Phi/Many Integrated Core (MIC) Related Web Page

Some Links to  Intel Xeon Phi/Many Integrated Core (MIC) Information
Many Integrated Core (MIC) Architecture - Advanced, Intel

Intel Xeon Phi Coprocessor Infographic (2012/06/19)
"Installing Intel Xeon Phi (MIC) in the PowerEdge C8220X"
 2012/09/19, jamonascone

"Dell Unveils First Shared Infrastructure Solution to Provide Hyperscale Customers
 with New Modular Computational and Storage Capabilities"
PowerEdge C8000 Customer Deployment Breaks New Ground
  "The Texas Advanced Computing Center (TACC) is leveraging the performance
   and flexibility benefits of the PowerEdge C8000 series in its new supercomputer
   "Stampede," which is expected to become a model for supporting
   petascale-level computational science."

"How Xeon Phi Stacks Up to GPUs"
 September 25, 2012, Go Parallel

"First Xeon Phi Supercomputer to Launch on January 7th, 2013,
 Tesla K20 Inside too"
 9/13/2012, Bright Side of News *
  "... the Stampede deploys 2 PFLOPS of compute power through
   Sandy Bridge-EP based Xeon CPUs and no less than 7 PFLOPS using
   Xeon Phi "coprocessors"."
  "Furthermore, Center decided to pack 128 Tesla K20 (GK110-based) for
   visualization purposes"

With Presentation Slide Photo

"Programming and Compiling for Intel Many Integrated Core Architecture"
 08/23/2012, Intel Developer Zone

Compiler Methodology for Intel MIC Architecture
  "This methodology enables you to determine your application's suitability
   for performance gains using IntelR Many Integrated Core Architecture
   (Intel MIC Architecture)."

"Sandia's Arthur Pioneers MIC Supercomputers"
 August 31, 2012, Go Paralle

The U.S. Department of Energy's National Renewable Energy Laboratory (NREL)

"NREL Selects Partners for New High Performance Computer Data Center"
 NREL to work with HP and Intel to create one of the world's most energy efficient
 data centers.
 September 5, 2012
  "...a new energy-efficient high performance computer (HPC) system dedicated
   to energy systems integration, renewable energy research, and energy
   efficiency technologies."
  "The $10 million HPC system will reside at the Energy Systems Integration
   Facility (ESIF), under construction on the Golden, Colorado, campus."
  "The HPC data center at NREL is designed to be the world’s most energy
   efficient, with an annualized average power usage effectiveness (PUE)
   rating of 1.06 or better."
  "The HPC system will be deployed in two phases that will include scalable
   HP ProLiant SL230s and SL250s Generation 8 (Gen8) servers based on
   eight-core Intel Xeon E5-2670 processors as well as the next generation of
   servers featuring future 22nm Ivy Bridge architecture based Intel Xeon
   processors and Intel Many Integrated Core architecture based IntelR Xeon Phi
   co-processors. The first phase of the HPC installation will begin in
   November 2012, reaching petascale capacity in the summer of 2013.
   HP and Intel were selected after a competitive, open procurement process."

"Intel Xeon Processors and Xeon Phi Co-Processors Promise to Power
 World's Most Efficient HPC Data Center"
 2012/09/05, IntelPR : News Stories
  "...The system is scheduled to deliver full compute capacity in the summer of
   2013 and will feature approximately 3,200 Intel XeonR processors including
   current-generation Intel Xeon processor E5-2670, future 22nm Ivy Bridge based
   processors and approximately 600 new IntelR Xeon Phi co-processors. The total
   peak performance of the system is expected to exceed 1 Petaflop ..."

"NREL Selects HP For New HPC System"
 September 5, 2012, Marc Hamilton's Blog
 Marc Hamilton ? Hyperscale Business Unit, HP Enterprise Group.

"HP, Intel Score Petaflop Supercomputer at DOE Lab"
 September 05, 2012, Michael Feldman, HPCwire
  "Warm is the keyword here. Intake water for the computing equipment is
   around room temperature -- 75F or thereabouts. Water exiting the servers
   is approximately 95F and, at NREL, will be recycled to heat the facility.
   Hammond says that in the future they plan to export the server-warmed water
   to other buildings on the rest of the campus."
  Steve Hammond, NREL's Computational Science director

"US energy lab's pump-happy petaflopper goes green"
 Shiny new Xeon-Xeon Phi hybrid splashes into water-cooled data center
 5th September 2012, The Register
  "Hammond says that the data center will have no mechanical chillers and
   will only use evaporative cooling, which is a choice you can make in the dry
   Colorado air. The design that HP and Intel have come up for the SL server
   nodes is capable of taking away about 90 per cent of the heat generated
   by the servers, leaving that evaporative cooling to only have to cope with
   the remaining 10 per cent of the load on the server side."

  "The water-cooling system is configured to bring 75-degree water to
   the server components and to run with a 95-degree return temperature into
   the evaporative coolers that chill the water and the air inside the data center
   as well."
  Steve Hammond, NREL's Computational Science director

"Scientists Benchmark MIC Workloads for Xeon Phi"
 August 29, 2012, Go Parallel

"Hybrid Message Passing and Threading for Heterogeneous Use on CPUs
 and the IntelR Many Integrated Core (MIC) Architecture"
 Vincent Betro, National Institute for Computational Sciences
 Extreme Scaling Workshop 2012

Extreme Scaling Workshop 2012, July 15 and 16, 2012

"Intel teaches Xeon Phi x86 coprocessor snappy new tricks"
 The interconnect rings a bell
 5th September 2012, The Register

"Intel details Knights Corner architecture at long last"
 Hot Chips 2012: From GPU to soap opera to product
 Aug 28, 2012, SemiAccurate

"Intel Parts the Curtains on Xeon Phi... A Little Bit"
 August 28, 2012, Michael Feldman, HPCWire

"What does Intel’s choice of GDDR5 graphics DRAM for main memory with
 its Manycore Xeon Phi coprocessor say about SoC design?"
 August 28, 2012, Denali Memory Report

"Intel gives peek inside Xeon Phi at Hot Chips"
 8/28/2012, Rick Merritt, EETimes

"Chip Shot: Intel Reveals Architecture Details of Intel Xeon Phi Co-Processor"
 2012/08/30, Radek : News Stories, Intel
HotChips 2012 presentation
"Intel Xeon Phi coprocessor
 (codename Knights Corner)"
 George Chrysos
 Senior Principal Engineer
 Hot Chips, August 28, 2012

"Under the Armor of Knights Corner:  Intel MIC Architecture at Hotchips 2012"
 2012/08/30, George Chrysos : The Data Stack, Intel

"Tracking Xeon Phi's Roots"
 August 06, 2012, Robert Gelber, HPCwire
*)Full story at VR-Zone

"Intel Xeon Phi (B0 Stepping): The Knight in Shining Armor?"
 July 31 2012,

"Intel's 50-core champion: In-depth on Xeon Phi"
 July 30, 2012, ExtreameTech

Electronic Structure Calculation Methods on Accelerators
 February 6-8, 2012, OLCF Workshops, Training
"An Overview of Intel Many Integrated Core (Intel MIC) Architecture"
 James Jeffers (Intel)
"Early Application Experiences with the Intel MIC Architecture"
 Glenn Brook (NICS)

"Virtualized Symmetric Multiprocessing Eases MIC Transition"
 July 24, 2012, Go Parallel
  "ScaleMP virtualizes dual Xeon E5-2600 processors with 128 Gbytes and
   a 50-core Xeon Phi coprocessor board with 8 Gbytes of memory, making it
   appear to programmers as a virtual SMP with a 66-core Xeon processor
   and 136 Gbytes of memory." Source: ScaleMP

"'First of a Kind' Experimental Cluster based on Intel MIC Architecture"
 June 25, 2012, Appro Blog

"ISC'12 Interview with Sandia National Laboratory- Experimental MIC Cluster"
 2012/07/26, ApproSupercomputers
  "Jim Ang from Sandia National Laboratories (SNL) is interviewed here
   during the ISC Conference in Hamburg, Germany June 2012."

"Advanced Architecture Test Beds,"
 Suzanne M. Kelly, James A. Ang, and James H. Laros III
 Sandia National Laboratories, White Paper, March 2012

CCIM Publications and Presentations
Computation, Computers, Information and Mathematics (CCIM)
Sandia National Laboratories

"ispc: A SPMD Compiler with Xeon and Xeon Phi support"
 27 July 2012, GPU Science

"ispc: Xeon and Xeon Phi support now"
 July 27, 2012, Software Blog, Intel
"ispc: A SPMD Compiler for High-Performance CPU Programming"
 Matt Pharr and Bill Marks
 InPar 2012, May 13-14, 2012
 "best paper award"

Intel SPMD Program Compiler
Compiling For The Intel Xeon Phi Architecture

Matt Pharr, Principal Engineer at Intel
"ispc: A SPMD Compiler for High-Performance CPU Programming"
 Matt Pharr and Bill Marks
 InPar 2012, May 13-14, 2012
 Talk Slide

InPar, May 13-14, 2012

"Details announced of Pawsey Centre supercomputer procurement"
 20 July 2012
  "iVEC and CSIRO have welcomed today’s announcement by Minister for
   Science and Research, Senator Chris Evans, of the new supercomputer
   to be installed at the Pawsey Centre in Perth."

Cray Cascade system
 2013: 0.3 petaflops
 2014: More than 1.2 petaflops, using a combination of Intel Ivy Bridge,
       Haswell and MIC processors

CSIRO (Commonwealth Scientific and Industrial Research Organisation)

"Cray Signs Contract to Install Cascade Supercomputer and Sonexion
 Storage System at the Pawsey Centre"
 Jul 24, 2012
"Cray bags $21m Cascade super deal down under"
 Xeon, Xeon Phi hybrid to do radio astronomy
 24th July 2012, The Register

"Xeon Phi Lacks Binary Compatibility, Breaks AMD64 Conventions"
 7/13/2012, Bright Side Of News*

[san-tech][03578] Slide: International Workshop on Runtime and Operating Systems for Supercomputers (ROSS 2012), (2012/06/29)

"Intel Xeon Phi to Provide Easy Access to Parallelism"
 2012/07/10, RichReport, Recorded at ISC'12 in Hamburg.

"ScaleMP vSMP Foundation to Support Intel Xeon Phi"
 2012/06/23, RichReport, 4:26
"Video: ScaleMP to Support Intel Xeon Phi Coprocessors"
 Jun 23, 2012, insideHPC

"Allinea Software unveils support for IntelR XeonR Phi? Product Family at ISC12"
 Jun 18, 2012

"ScaleMP vSMP Founation to Support Intel Xeon Phi"
 Virtualized Intel Many Integrated Core architecture based products allows
 for transparent programming and support for large-memory applications

"Intel Xeon Phi coprocessors accelerate the pace of discovery and innovation"
 June 18, 2012, Raj Hazra, Technology@Intel

Intel Xeon Phi Coprocessor Infographic

International Supercomputing Conference 2012
"The Explosion of Petascale in the Race to Exascale"
 Rajeeb Hazra, VP, Intel Architecture Group, GM, Technical Computing
 Intel Corporation

"Intel slaps Xeon Phi brand on MIC coprocessors"
 18th June 2012, The Register
"Nvidia shows off Tesla K10 performance"
 18th June 2012, The Register
"Intel Xeon Phi comes in at 150 in the Top 500 list"
 Jun 18 2012, Inquirer
"For Intel, the Future of Supercomputing is Phi"
 June 18th, 2012, Data Center Knowledge
"Intel Says More About Supercomputer Chip, Including Brand"
 June 18, 2012, WSJ

Rank 150@June 2012, Top500
Discovery - Intel Cluster, Xeon E5-2670 8C 2.600GHz, Infiniband FDR, Intel MIC

  Site: Intel
  System URL:
  Manufacturer: Intel
  Cores: 9800
  Power: 100.80 kW
  Memory: 8960 GB
  Interconnect: Infiniband FDR
  Operating System: Linux

"Cray to Add Intel Xeon Phi Coprocessors to Its Next-Generation "Cascade" Supercomputer"
 Jun 18, 2012, Cray Inc.

"Intel Releases Knights Corner ISA, Lays Groundwork for MIC Launch"
 June 11, 2012, Michael Feldman, HPCwire

Intel > Forums > Intel Many Integrated Core (MIC) Architecture
RESOURCES (including downloads)
Parallel Programming open source MIC Intel Many Integrated Core (Tag)

Knights Corner micro-architecture related information: Documents
"Knights Corner Instruction Set Reference Manual", June 6, 2012
"ABI document System V Application Binary Interface
 K1OM Architecture Processor Supplement",Version1.0, April 26, 2012
"Knights Corner Performance Monitor Units", Version1.0, May 21, 2012

"Knights Corner micro-architecture support"
 June 5, 2012, James Reinders, Intel Software Blogs

Knights Corner micro-architecture support
*)Linux and Tools
*)Low-level programming documentation
*)Twice the bang from a single optimization effort
*)Coprocessor that is powerful enough to boot Linux

"Knights Corner: Open source software stack"
 June 5, 2012, James Reinders, Intel Software Blogs

*)MPSS (Intel Many Integrated Core (MIC) Platform Software Stack)
*)GCC: the basics are in
*)GDB: ready for C and C++ developers
*)Linux support for Knights Corner

"TACC symposium and programming two SMP-on-a-chip devices"
 April 26, 2012, James Reinders, Intel Software Blogs

[san-tech][03544] Slide/Paper: TACC-Intel Highly Parallel Computing Symposium (2012/04/10, 11) 
"TACC-Intel Symposium Highlights MIC Architecture Developments"
 May 01, 2012, HPCwire
TACC-Intel Highly Parallel Computing Symposium
 April 10th-11th, 2012

"New Paper: An Early Evaluation of the Scalability of Graph Algorithms
 on the Intel MIC Architecture"
 Published April 29, 2012,

"Intel MIC for Business Applications?"
 April 17, 2012, HPCwire

2012年 4月 16日, ■後藤弘茂のWeekly海外ニュース■

2012年 4月 17日, ■後藤弘茂のWeekly海外ニュース■

"Intel's 50+ core MIC architecture: HPC on a Card or Massive Co-Processor?"
  April 10, 2012, Dr. Dobbs

"The Processors of Petascale"
 April 10, 2012, HPCwire

"No Free Lunch for Intel MIC (or GPU's)"
 On Apr 3 2012, Steve Scott, NVIDIA Blog

"NVIDIA Pokes Holes in Intel's Manycore Story"
 April 03, 2012, HPCwire

"Nvidia: No magic compilers for HPC coprocessors"
 No free lunch for MIC, either
 3rd April 2012, The Register

"東大のPost T2Kスパコン、IntelのMICの採用を検討"
 2012/02/20, マイナビニュース

[san-tech][03477] Slide: Rice 2012 Oil & Gas HPC Workshop (March 1, 2012)

"Advances in HPC for Oil and Gas: The Intel MIC Architecture"
 Lars Koesterke and Yaakoub El-Khamra
 The University of Texas at Austin

"New Data Center Construction Timelapse"
 2012/03/29, TACCutexas, 1:01, 1080p

"Vectorization - Find out what it is, Find out More!"
 January 31, 2012, Blog, Intel Software Network

"The Best of HPC and Supercomputing in 2011: Efficiency, Performance and Intel MIC"

"MIC: Stepping-stone to Quantum Computing?"
 December 14, 2011, Blog, Intel Software Network

"TACC Expands Datacenter for Stampede Supercomputer"
 December 07, 2011, HPCwire
"TACC Data Center Expansion"
 2011/12/02, TACCutexas, 2:47, 1080p

"MIC architecture support by software tools - SC11 wrap-up"
 November 17, 2011, Blog, Intel Software Network

"quick chat about MIC architecture with Mike Dewar, NAG"
 November 17, 2011, Blog, Intel Software Network

"Seeing One TeraFlop/sec, the software side, and feeling a bit emotional"
 November 17, 2011, Blog, Intel Software Network

"Hot Intel teraflops MIC coprocessor action in a hotel"
 Sweet nothings whispered about Xeon E5 performance
 16th November 2011, The Register

"Intel Sets High Water Mark of One Teraflop with 'Knights Corner'"
 November 16, 2011, HPCwire

"Supercomputing 2011 Day 2: Knights Corner shown at 1TF Per Socket"

"Intel Reveals Details of Next-Generation High-Performance Computing Platforms"

"TACC to Highlight HPC and Visualization Technologies at SC11"
 November 09, 2011, HPCwire

"IDC Report Bullish on Heterogeneous Computing"
 November 09, 2011, HPCwire

"Appro Boosts Flagship Product Line with Latest CPUs, Accelerators"
 November 02, 2011, HPCwire

"Adapteva Builds Manycore Processor That Will Deliver 70 Gigaflops/Watt"
 October 03, 2011, HPCwire

""Stampede's" Comprehensive Capabilities to Bolster U.S. Open Science
 Computational Resources"
 Texas Advanced Computing Center's new supercomputer to enable
 traditional HPC, data-intensive computing, and scientific visualization
 for nation's scientists

"Intel MIC Scores 1st Home Run with 10 Petaflop “Stampede” Supercomputer"

"Dell to Build 10-Petaflop Supercomputer For Science"
 September 22, 2011, HPCwire

"Intel Takes a Bite Out of NVIDIA's HPC Business"
 September 22, 2011

"Dell, Intel rope Texas-sized 10 petaflopper"
 Xeon E5 and many-core MIC inside
 22nd September 2011, The Register
"Justin Rattner氏キーノートスピーチ
 2011年 9月 20日, 【IDF 2011レポート】

キーノートスピーチ Webcast (3件) はこちらで公開されています:
IDF Keynotes
"Intel shows linear scaling with MIC coprocessor"
 Army of Pentiums march in lockstep
 15th September 2011, The Register
"CERN HLT Analysis of Intel Knights Ferry on High Energy Physics"
 2011/07/11, RichReport, 6:05, 1080p

  "In this video, CERN demonstrates performance results from prototype
   Knights Ferry hardware on its high energy physics applications"
"Demo: Linear Speedup on Intel Knights Ferry"
 2011/07/10, RichReport, 2:33, 1080p

  "In this video, Intel demonstrates linear speedups on Knights Ferry on
   Molecular Dynamics"
"Better Together: Intel Demo Shows App Performance Xeon with Knights Ferry"
 2011/07/07, RichReport, 4:15, 1080p

  "In this video, Intel's Chief Software Evangelist James Reinders describes
   the company' Knights Ferry demo at ISC'11."

"Intel MIC architecture for TifaMMy, a Cache-oblivious Matrix-matrix Multiplication"
 2011/07/08, RichReport, 1:33, 1080p

  "In this video, Alexander Heinecke from the Technical University of Munich
   demonstrates the advantages of the Intel MIC architecture for TifaMMy,
   a cache-oblivious Matrix-matrix Multiplication code."

> Presentation:
> "Intel: Accelerating the Path to Exascale"
>  Kirk Skaugen
>  Vice President Intel Architecture Group
>  General Manager Data Center Group

"Intel Press Briefing-- New Exascale Initiative"
 2011/06/22, RichReport, 29:24, 480p

  "At ISC'11, Kirk Skaugen, Intel Corporation vice president and
   general manager of the Data Center Group, outlined the company's
   vision to achieve ExaFLOP/s performance by the end of this decade.
   An ExaFLOP/s is quintillion computer operations per second,
   hundreds times more than today's fastest supercomputers. With
   collaboration partners, Intel aims to deliver complete technology
   solution for exascale performance by the end of the decade."


"Evaluating the Intel MIC Architecture"
 Arndt Bode, Leibniz Supercomputing Centre (lrz), Germany

の発表まで。それに続く SGIに発表は

> SGI CTO Eng Lim Goh博士のビデオ:
> "SGI Picks the Intel MIC Swim Lane for Exascale by 2018"
>  2011/06/20, RichReport, 5:46, 480p
>   "In this video, SGI's Dr. Eng Lim Goh presents the company's plans
>    to use the Intel MIC architecture on the road to Exascale computing
>    by 2018. Recorded at the Intel Exascale briefing at ISC'11 in
>    Hamburg on June 20, 2011."

"Video: Intel Expects to Achieve Exascale Performance Benchmark"
 06.22.2011, insideHPC
[san-tech][03205] Video: Kirk Skaugen, Intel at ISC'11 (Re: Intel Many Integrated Core (Intel MIC) Architectureプレスリリース資料等@ISC 2011)
  Date: Fri, 24 Jun 2011 00:30:16 +0900
[san-tech][03192] Intel Many Integrated Core (Intel MIC) Architectureプレスリリース資料等@ISC 2011
  Date: Tue, 21 Jun 2011 10:33:06 +0900
[san-tech][03066] Intel、3次元トライゲートトランジスタ プレス資料 (PDF) 等
  Date: Fri, 06 May 2011 00:15:38 +0900
[san-tech][02944] Intel Single-chip Cloud Computer (SCC) On-chip Interconnect評価
  Date: Tue, 08 Feb 2011 14:35:36 +0900
[san-tech][02860] Intel Many Integrated Core (MIC) at SC '10 (Re: Intel Larrabee路線変更)
  Date: Fri, 03 Dec 2010 08:45:17 +0900
[san-tech][02520] Re: Intel Larrabee路線変更
  Date: Sun, 08 Aug 2010 22:41:25 +0900
[san-tech][02353] Re: Intel Larrabee路線変更
  Date: Tue, 01 Jun 2010 17:30:55 +0900
[san-tech][02352] Re: Intel Larrabee路線変更
  Date: Tue, 01 Jun 2010 15:45:22 +0900
[san-tech][02332] Intel Larrabee路線変更,
  Date: Wed, 26 May 2010 12:34:02 +0900
[san-tech][02315] Re: Intel 48コアチップ (Single-chip Cloud Computer)
 Date: Sat, 22 May 2010 07:56:05 +0900
[san-tech][02200] Re: Intel 48コアチップ (Single-chip Cloud Computer) 
  Date: Fri, 09 Apr 2010 21:12:15 +0900
[san-tech][02179] Intel 48コアチップ (Single-chip Cloud Computer)
  Date: Sat, 27 Mar 2010 21:01:24 +0900
[san-tech][02042] Intel Larrabee講義資料 (2010/01/06)
  Date: Sat, 30 Jan 2010 01:54:18 +0900
[Links]: Intel Ivy Bridge Reviews, 2012/04/23 (22) & Intel acquires Cray's Interconnect Technology, 2012/04/24
[san-tech][03529] Slide: Intel Developer Forum (IDF) Beijing (April 11-12, 2012)
  Date: Mon, 16 Apr 2012 14:06:28 +0900
[san-tech][03525] Intel SSD 910 Series: PCIe-based 400GB and 800GB, April 12, 2012
  Date: Fri, 13 Apr 2012 01:36:10 +0900
[san-tech][03472] Intel Ethernet Controller x540 related URLs
  Date: Thu, 08 Mar 2012 20:17:23 +0900

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